How Mixed Stress Conditions Affect Single Oxide Defects in MOSFETs

The international roadmap for semiconductors lists bias temperature instability (BTI) and hot-carrier (HC) degradation as most difficult challenges, which should be properly understood and modeled. Although extensive experimental and theoretical studies of these phenomena have been performed there are still open issues in understanding the nature and behavior of material defects contributing to BTI and HCD. Even more dramatic, in circuits transistors are rarely subjected to idealized BTI or HC conditions. Thus we focus on the impact of mixed negative BTI (NBTI) and HC stress on material defects in pMOSFETs. In order to characterize recoverable device degradation, we record the behavior of oxide defects at mixed stress conditions.

Degradation mechanisms are caused by material defects in the amorphous gate oxide of a MOSFET. The defects can capture or emit charge carriers from the substrate and from the gate oxide. The capture and emission events cause a change in the current between gate and source at constant gate-source voltage and drain-source voltage. This electrical response corresponds to an unwanted shift of the device characteristics, e.g., the threshold voltage. Measurements of these detrimental shifts allow us to characterize the impact of different stress conditions on the device characteristics and in the case of nano-scale MOSFETs to observe the nature of individual defects responsible for the unwanted shifts.

Time dependent defect spectroscopy measurements show that fewer defects contribute to the overall threshold voltage shift after mixed NBTI/HC stress than after pure NBTI stress. Although the electrostatic conditions at the source side hardly change for different stress modes at a fixed gate voltage, source side defects can show a completely different behavior after mixed NBTI/HC stress. This observation can be explained by considering that defect parameters can shift significantly at mixed stress conditions due to non-equilibrium processes. This occurs for all lateral positions and leads for example to a change of their capture and emission times. The consequence is that even if a defect captures a charge carrier during stress, it emits it immediately and remains neutral after stress. Thus, non-equilibrium processes have to be taken into account in existing defect models. Measurements and conclusions have been presented at the International Reliability Physics Symposium (IRPS) 2017 recently.

As a conclusion, our results suggest that non-equilibrium processes have to be taken into account to explain the behavior of defects responsible for the detrimental shifts of MOSFET parameters for mixed stress conditions. These results provide an insight in degradation processes in a more detailed way, which is a step towards a realistic MOSFET life time prediction under circuit operation.

Poster Presentation

Results and conclusions have been presented @ IRPS 2017

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